منابع مشابه
Full Adder Circuit . Part I
A set is pair if: (Def.1) There exist sets x, y such that it = 〈x, y〉. Let us mention that every set which is pair is also non empty. Let x, y be sets. Observe that 〈x, y〉 is pair. Let us mention that there exists a set which is pair and there exists a set which is non pair. Let us observe that every natural number is non pair. A set has a pair if: (Def.2) There exists a pair set x such that x ...
متن کاملFull Adder Circuit. Part II
In this article we continue the investigations from [5] of verification of a design of adder circuit. We define it as a combination of 1-bit adders using schemes from [6]. n-bit adder circuit has the following structure 1st bit adder x 1 y 1 x 2 y 2 r 1 r 2 2nd bit adder nth bit adder x n y n r n As the main result we prove the stability of the circuit. Further works will consist of the proof o...
متن کاملFull Adder Circuit . Part I 1 Grzegorz
We introduce I1 has no pairs as an antonym of I1 has a pair. Observe that every set which is empty has also no pairs. Let x be a non pair set. Observe that {x} has no pairs. Let y be a non pair set. Note that {x,y} has no pairs. Let z be a non pair set. One can verify that {x,y,z} has no pairs. Let us observe that there exists a non empty set which has no pairs. Let X , Y be sets with no pairs....
متن کاملDesigning a Full Adder Circuit Based on Quasi-Floating Gate
Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full ad...
متن کاملComplementary Energy Path Adiabatic Logic based Full Adder Circuit
In this paper, we present the design and experimental evaluation of complementary energy path adiabatic logic (CEPAL) based 1 bit full adder circuit. A simulative investigation on the proposed full adder has been done using VIRTUOSO SPECTRE simulator of cadence in 0.18μm UMC technology and its performance has been compared with the conventional CMOS full adder circuit. The CEPAL based full adde...
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ژورنال
عنوان ژورنال: International Journal on Intelligent Electronic Systems
سال: 2014
ISSN: 0973-9238
DOI: 10.18000/ijies.30138